Programmable logic devices (PLDs) exist as a well-known type of integrated circuit (IC) that may be programmed by a user to perform specified logic functions. There are different types of programmable logic devices, such as programmable logic arrays (PLAs) and complex programmable logic devices (CPLDs). One type of programmable logic device, known as a field programmable gate array (FPGA), is very popular because of a superior combination of capacity, flexibility, time-to-market, and cost.
An FPGA typically includes an array of configurable logic blocks (CLBs) surrounded by a ring of programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a programmable interconnect structure. The CLBs, IOBs, and interconnect structure are typically programmed by loading a stream of configuration data (known as a bitstream) into internal configuration memory cells that define how the CLBs, IOBs, and interconnect structure are configured. An FPGA may also include various dedicated logic circuits, such as memories, microprocessors, digital clock managers (DCMs), and input/output (I/O) transceivers.
As feature size within an FPGA becomes smaller, especially for dense routing in sub-quarter micron fabricated integrated circuits, globally synchronous communication at high clock frequencies over long-haul routing within an FPGA, such as FPGA internal module-to-module routing, is becoming more problematic due at least in part to an increase in resistance-capacitance (RC) time constants. In some instances, the signal delay of all available paths of the interconnect structure from a source circuit to a sink circuit is incompatible with the desired clock period. That is, as clock frequencies and delays in the interconnect structure are increased, a signal may not be able to propagate from one circuit to another within a clock cycle.
Accordingly, there exists a need in the art for point-to-point communication between respective portions of an integrated circuit, such as an FPGA.